Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

– Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a standard domino circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a standard domino circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced. A low swing domino logic technique is proposed to decrease the dynamic switching power without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A circuit technique is proposed for reducing the standby leakage energy of domino logic circuits. The proposed circuit technique also enhances the delay and power characteristics of a domino circuit operating in the active mode. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The proposed circuit technique reduces the leakage energy by up to 207 times as compared to a standard low threshold voltage domino circuit. The sleep switch circuit technique exploits the full effectiveness of employing dual threshold voltage transistors to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The proposed circuit technique reduces the leakage energy by up to 58 times as compared to a standard dual threshold voltage domino circuit. With the proposed circuit technique, a domino adder enters and leaves the standby mode within a single clock cycle. The energy overhead of the sleep switch circuit technique is low, justifying the activation of the proposed sleep scheme during idle periods as short as 539 clock cycles.